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author | Jeremy Compostella <jeremy.compostella@intel.com> | 2023-08-30 15:35:46 -0700 |
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committer | Julius Werner <jwerner@chromium.org> | 2023-09-14 21:01:56 +0000 |
commit | 79f2e1fc8b6192e96f99c05f71baeb77d4633d40 (patch) | |
tree | 4433e9b91f743d9950521c694fd2ef5217eb4df9 /src/cpu/intel/model_68x | |
parent | c9cae530e5ac54c5b3639d0d555966ca5cad65ff (diff) |
cbfstool: Make add-stage support multiple loadable segments
For x86 eXecute-In-Place (XIP) pre-memory `.data` section support, we
have to use an extra segment as the VMA/LMA of the data is different
than the VMA/LMA of the code.
To support this requirement, this patch makes cbfstool:
1. Allow the load of an ELF with an extra segment
2. Makes add-stage for XIP (cf. parse_elf_to_xip_stage()) write its
content to the output binary.
To prevent the creation of unsuitable binaries, cbfstool verifies that
the LMA addresses of the segments are consecutives.
TEST=XIP pre-memory stages with a `.data` section have the `.data`
section covered by a second segment properly included right after
the code.
Change-Id: I480b4b047546c8aa4e12dfb688e0299f80283234
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77584
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_68x')
0 files changed, 0 insertions, 0 deletions