diff options
author | Michael Niewöhner <foss@mniewoehner.de> | 2020-10-11 14:05:32 +0200 |
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committer | Nico Huber <nico.h@gmx.de> | 2020-10-24 09:46:45 +0000 |
commit | 10ae1cf2cda38e681849dcc9e6e86ee3330a8b17 (patch) | |
tree | e71fa6148adb9895fbc02111a74a35b395a0794e /src/cpu/intel/model_2065x/model_2065x_init.c | |
parent | 29a52c8308ab270c46c1d859db308ba1de5d1e81 (diff) |
{cpu,soc}/intel: deduplicate cpu code
Move a whole bunch of copy-pasta code from soc/intel/{bdw,skl,cnl,icl,
tgl,ehl,jsl,adl} and cpu/intel/{hsw,model_*} to cpu/intel/common.
This change just moves the code. Rework is done in CB:46588.
Change-Id: Ib0cc834de8492d59c423317598e1c11847a0b1ab
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46274
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/intel/model_2065x/model_2065x_init.c')
-rw-r--r-- | src/cpu/intel/model_2065x/model_2065x_init.c | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 65b28c0a0e..db433536cf 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -148,15 +148,6 @@ static void configure_misc(void) wrmsr(IA32_THERM_INTERRUPT, msr); } -static void enable_lapic_tpr(void) -{ - msr_t msr; - - msr = rdmsr(MSR_PIC_MSG_CONTROL); - msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ - wrmsr(MSR_PIC_MSG_CONTROL, msr); -} - static void set_max_ratio(void) { msr_t msr, perf_ctl; |