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authorArthur Heymans <arthur@aheymans.xyz>2019-01-05 17:18:11 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-11 10:19:16 +0000
commitc6bf74ec757b4445a14179a9960d4532fd0eb479 (patch)
treed77e1f701d9cabe0757325236ab63966061f222c /src/cpu/intel/microcode
parenta706ad54446afc418c60776c06e699943ce4bdd5 (diff)
cpu/intel/microcode: Support update before CAR entry
Change-Id: Ie3c2d2e1bc79dcaffd9901e17f83ceeaabd1d659 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/cpu/intel/microcode')
-rw-r--r--src/cpu/intel/microcode/Kconfig7
-rw-r--r--src/cpu/intel/microcode/Makefile.inc7
2 files changed, 10 insertions, 4 deletions
diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig
new file mode 100644
index 0000000000..b78389215d
--- /dev/null
+++ b/src/cpu/intel/microcode/Kconfig
@@ -0,0 +1,7 @@
+config MICROCODE_UPDATE_PRE_RAM
+ bool
+ depends on SUPPORT_CPU_UCODE_IN_CBFS
+ default y if C_ENVIRONMENT_BOOTBLOCK
+ help
+ Select this option if you want to update the microcode
+ during the cache as ram setup.
diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc
index f589430771..2df1d5eb6f 100644
--- a/src/cpu/intel/microcode/Makefile.inc
+++ b/src/cpu/intel/microcode/Makefile.inc
@@ -1,6 +1,5 @@
-################################################################################
-## One small file with the awesome super-power of updating the CPU microcode
-## directly from CBFS. You have been WARNED!!!
-################################################################################
+bootblock-$(CONFIG_MICROCODE_UPDATE_PRE_RAM) += microcode_asm.S
+romstage-$(CONFIG_MICROCODE_UPDATE_PRE_RAM) += microcode_asm.S
+
ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c
romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c