diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-18 07:39:31 +0300 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-06 12:29:19 +0000 |
| commit | 730df3cc43d76d830f6c88441d8bea75b9047a6c (patch) | |
| tree | 2272d885de331209f3a3b869d84f089cf27e3fde /src/cpu/intel/haswell | |
| parent | 42e422ed66e3057683c4ada29442a36a75e418ba (diff) | |
arch/x86: Make RELOCATABLE_RAMSTAGE the default
No need to provide an option to try disable this.
Also remove explicit ´select RELOCATABLE_MODULES'
lines from platform Kconfigs.
Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/intel/haswell')
| -rw-r--r-- | src/cpu/intel/haswell/Kconfig | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 9076b88015..423966c2d4 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -18,8 +18,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select TSC_CONSTANT_RATE select SMM_TSEG - select RELOCATABLE_MODULES - select RELOCATABLE_RAMSTAGE select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE @@ -46,7 +44,6 @@ config SMM_RESERVED_SIZE config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n - depends on RELOCATABLE_RAMSTAGE help The haswell romstage code caches the loaded ramstage program in SMM space. On S3 wake the romstage will copy over a fresh |