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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-10-29 01:33:25 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-30 17:44:10 +0100 |
| commit | 5c5c4a694314d9b2a6d085fb97770d0ee12cc17c (patch) | |
| tree | df9cdab1c0099d8c9a993dd1833548c542d77e49 /src/cpu/amd | |
| parent | e3b5d36321216cbeef48f18768eafaea915ea691 (diff) | |
cpu/amd/model_fxx: Clear out unused / stale MTRRs in ramstage
This mirrors a similar commit made to Family 10h support
in changeset 11966 file model_10xxx_init.c
TEST: Booted ASS KFSN4-DRE with 1x Opteron 8222
Change-Id: I760ef27be00aed11c0ac21b9bd741189f4b05834
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12250
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/amd')
| -rw-r--r-- | src/cpu/amd/model_fxx/model_fxx_init.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index db936f8933..93fa07f961 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -460,6 +460,18 @@ static void model_fxx_init(device_t dev) /* Turn on caching if we haven't already */ x86_enable_cache(); + + /* Initialize all variable MTRRs except the first pair */ + msr.hi = 0x00000000; + msr.lo = 0x00000000; + + disable_cache(); + + for (i = 0x2; i < 0x10; i++) { + wrmsr(0x00000200 | i, msr); + } + + enable_cache(); amd_setup_mtrrs(); x86_mtrr_check(); |