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authorFelix Singer <felix.singer@secunet.com>2020-04-06 10:45:25 +0200
committerNico Huber <nico.h@gmx.de>2020-04-07 11:15:13 +0000
commit66579d4e362bb640a9c9e2d960d72c6c37ff67cc (patch)
tree196b212d8b461b6cd0dbeadcd25fb272ab5079a3 /src/cpu/amd
parentecaa2d4741696ab0228500fd170e58ee4d268353 (diff)
sb/intel/bd82x6x/sata: Don't hard-code values
The interrupt line registers are configured in a central place, pch_pirq_init() in `lpc.c`, according to the PIRQ configuration. Hardcoding values here makes no sense. Change-Id: Ide5f101b2e5bda84f3c2ff8c8ca636b8233bb948 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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