- To reduce confuse rename the parts of linuxbios bios that run from

  ram linuxbios_ram instead of linuxbios_c and linuxbios_payload...
- Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86
- ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB.
- Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work.
- Start using romcc's built in preprocessor (This will simplify header compiler checks)
- Add helper functions for examining all of the resources
- Remove debug strings from chip.h
- Add llshell to src/arch/i386/llshell (Sometime later I can try it...)
- Add the ability to catch exceptions on x86
- Add gdb_stub support to x86
- Removed old cpu options
- Added an option so we can detect movnti support
- Remove some duplicate definitions from pci_ids.h
- Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic
- Minor romcc bug fixes


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

4 files changed, 48 insertions, 44 deletions

diff --git a/src/cpu/amd/model_fxx/Config.lb b/src/cpu/amd/model_fxx/Config.lb
index 044fe8670f..bf7b9987cc 100644
--- a/src/cpu/amd/model_fxx/Config.lb
+++ b/src/cpu/amd/model_fxx/Config.lb
@@ -1,5 +1,7 @@
 uses HAVE_INIT_TIMER
+uses HAVE_MOVNTI
 default HAVE_INIT_TIMER=1
+default HAVE_MOVNTI=1
 dir /cpu/x86/tsc
 dir /cpu/x86/fpu
 dir /cpu/x86/mmx
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 0247fd00d3..506e017457 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -75,13 +75,41 @@ static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char
 	}
 }
 
+struct mem_state {
+	unsigned long mmio_basek, tomk;
+};
+static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resource *res)
+{
+	struct mem_state *state = gp;
+	unsigned long topk;
+	unsigned int start_mtrr;
+	unsigned int last_mtrr;
+
+	topk = resk(res->base + res->size);
+	if (state->tomk < topk) {
+		state->tomk = topk;
+	}
+	if ((topk < 4*1024*1024) && (state->mmio_basek < topk)) {
+		state->mmio_basek = topk;
+	}
+	start_mtrr = fixed_mtrr_index(resk(res->base));
+	last_mtrr  = fixed_mtrr_index(resk((res->base + res->size)));
+	if (start_mtrr >= NUM_FIXED_RANGES) {
+		return;
+	}
+	printk_debug("Setting fixed MTRRs(%d-%d) Type: WB\n",
+		start_mtrr, last_mtrr);
+	set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);
+	
+}
+
+
 #endif
 
 void amd_setup_mtrrs(void)
 {
-	unsigned long mmio_basek, tomk;
+	struct mem_state state;
 	unsigned long i;
-	device_t dev;
 	msr_t msr;
 
 	/* Enable the access to AMD RdDram and WrDram extension bits */
@@ -99,54 +127,29 @@ void amd_setup_mtrrs(void)
 	 * significant holes in the address space, so just account
 	 * for those two and move on.
 	 */
-	mmio_basek = tomk = 0;
-	for(dev = all_devices; dev; dev = dev->next) {
-		struct resource *res, *last;
-		last = &dev->resource[dev->resources];
-		for(res = &dev->resource[0]; res < last; res++) {
-			unsigned long topk;
-			unsigned long start_mtrr, last_mtrr;
-			if (!(res->flags & IORESOURCE_MEM) ||
-				(!(res->flags & IORESOURCE_CACHEABLE))) {
-				continue;
-			}
-			topk = resk(res->base + res->size);
-			if (tomk < topk) {
-				tomk = topk;
-			}
-			if ((topk < 4*1024*1024) && (mmio_basek < topk)) {
-				mmio_basek = topk;
-			}
-
-			start_mtrr = fixed_mtrr_index(resk(res->base));
-			last_mtrr  = fixed_mtrr_index(resk(res->base + res->size));
-			if (start_mtrr >= NUM_FIXED_RANGES) {
-				continue;
-			}
-			printk_debug("Setting fixed MTRRs(%d-%d) Type: WB\n",
-				start_mtrr, last_mtrr);
-			set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);
-		}
-	}
+	state.mmio_basek = state.tomk = 0;
+	search_global_resources(
+		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
+		set_fixed_mtrr_resource, &state);
 	printk_debug("DONE fixed MTRRs\n");
-	if (mmio_basek > tomk) {
-		mmio_basek = tomk;
+	if (state.mmio_basek > state.tomk) {
+		state.mmio_basek = state.tomk;
 	}
-	/* Round mmio_basek down to the nearst size that will fit in TOP_MEM */
-	mmio_basek = mmio_basek & ~TOP_MEM_MASK_KB;
-	/* Round tomk up to the next greater size that will fit in TOP_MEM */
-	tomk = (tomk + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB;
+	/* Round state.mmio_basek down to the nearst size that will fit in TOP_MEM */
+	state.mmio_basek = state.mmio_basek & ~TOP_MEM_MASK_KB;
+	/* Round state.tomk up to the next greater size that will fit in TOP_MEM */
+	state.tomk = (state.tomk + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB;
 
 	disable_cache();
 
 	/* Setup TOP_MEM */
-	msr.hi = mmio_basek >> 22;
-	msr.lo = mmio_basek << 10;
+	msr.hi = state.mmio_basek >> 22;
+	msr.lo = state.mmio_basek << 10;
 	wrmsr(TOP_MEM, msr);
 
 	/* Setup TOP_MEM2 */
-	msr.hi = tomk >> 22;
-	msr.lo = tomk << 10;
+	msr.hi = state.tomk >> 22;
+	msr.lo = state.tomk << 10;
 	wrmsr(TOP_MEM2, msr);
 
 	/* zero the IORR's before we enable to prevent
diff --git a/src/cpu/amd/socket_940/Config.lb b/src/cpu/amd/socket_940/Config.lb
index 9f0e6c689a..4b23f0b46a 100644
--- a/src/cpu/amd/socket_940/Config.lb
+++ b/src/cpu/amd/socket_940/Config.lb
@@ -1,3 +1,3 @@
-config chip.h
-object socket_940.o
+#config chip.h
+#object socket_940.o
 dir /cpu/amd/model_fxx
diff --git a/src/cpu/amd/socket_940/socket_940.c b/src/cpu/amd/socket_940/socket_940.c
index d62834f4e7..46d0cbd449 100644
--- a/src/cpu/amd/socket_940/socket_940.c
+++ b/src/cpu/amd/socket_940/socket_940.c
@@ -3,5 +3,4 @@
 
 
 struct chip_operations cpu_amd_socket_940_ops = {
-	.name = "socket 940",
 };