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authorStefan Reinauer <stepan@coresystems.de>2010-02-25 13:40:49 +0000
committerStefan Reinauer <stepan@openbios.org>2010-02-25 13:40:49 +0000
commita7acc515bd10f24d400b3aa3a3c807076cac4f95 (patch)
treeb177d2bff5eceb06ce47f90b743ddcf04ffa80fd /src/cpu/Kconfig
parent3a54ac9c362d2e5900edd7e1c459ffea1e29df64 (diff)
HAVE_MOVNTI really means SSE2. Also add sfence in the MOVNTI case.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/Kconfig')
-rw-r--r--src/cpu/Kconfig18
1 files changed, 15 insertions, 3 deletions
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index 3c4c41967f..c0cf76887f 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -32,14 +32,26 @@ config SMP
This option is used to enable certain functions to make coreboot
work correctly on symmetric multi processor (SMP) systems.
-# Set MMX and SSE in socket or model if the CPU has them.
-# If all CPUs for the socket have MMX or SSE, set them there.
-# These options are only needed for boards compiled with romcc.
config MMX
bool
+ help
+ Select MMX in your socket or model Kconfig if your CPU has MMX
+ streaming SIMD instructions. ROMCC can build more efficient
+ code if it can spill to MMX registers.
config SSE
bool
+ help
+ Select SSE in your socket or model Kconfig if your CPU has SSE
+ streaming SIMD instructions. ROMCC can build more efficient
+ code if it can spill to SSE (aka XMM) registers.
+
+config SSE2
+ bool
+ help
+ Select SSE2 in your socket or model Kconfig if your CPU has SSE2
+ streaming SIMD instructions. Some parts of coreboot can be built
+ with more efficient code if SSE2 instructions are available.
config VAR_MTRR_HOLE
bool