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| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-04-29 19:25:07 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2020-05-04 22:45:16 +0000 |
| commit | e7a083ec3dc0d7696cf6a0eda03dac67d6936834 (patch) | |
| tree | f702e193c781a82a5e8b57fa2bb80c5bb6ca9804 /src/commonlib/mem_pool.c | |
| parent | 4eadcb053795514ad6fdd61b0b9a95729dee8bd0 (diff) | |
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3163
Update FSP headers for Tiger Lake platform generated based FSP
version 3163. Which includes below additional UPDs:
FSPM:
-BootFrequency
-SerialIoUartDebugMode
FSPS:
-PcieRpPmSci
-PchPmWoWlanEnable
-PchPmWoWlanDeepSxEnable
-PchPmLanWakeFromDeepSx
BUG=b:155315876
BRANCH=none
TEST=build and boot ripto/volteer
Cq-Depend: chrome-internal:2944102
Cq-Depend: chrome-internal:2939733
Cq-Depend: chrome-internal:2943140
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ida87ac7dd7f5fd7ee0459ae1037a8df816976083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40898
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/commonlib/mem_pool.c')
0 files changed, 0 insertions, 0 deletions