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authorYuchi Chen <yuchi.chen@intel.com>2024-09-09 09:53:38 +0800
committerLean Sheng Tan <sheng.tan@9elements.com>2024-11-09 10:21:25 +0000
commitf8d4283e78d2df2d63ba8994395b2fc0ee2c84bc (patch)
tree759b9df8cbf1427f914920413762bf072448bc57 /src/arch
parent60771bfdb102be639b7f074299c5778a8d9b24b9 (diff)
arch/x86: Define macros for hard-coded HPET registers
HPET General Capabilities and ID Register at offset 0x0 and Timer 0 Configuration and Capability Register at offset 0x100 are used to determine the generation of HPET ACPI tables. This patch adds macro definitions for these registers and fields. Definitions are from IA-PC HPET (High Precision Event Timers) Specification Revision 1.0a. Change-Id: I31413afcbfc42307e3ad3f99d75f33f87092d7aa Signed-off-by: Yuchi Chen <yuchi.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84252 Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/x86/include/arch/hpet.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/arch/x86/include/arch/hpet.h b/src/arch/x86/include/arch/hpet.h
index 224279eb6f..7c2e44ffb9 100644
--- a/src/arch/x86/include/arch/hpet.h
+++ b/src/arch/x86/include/arch/hpet.h
@@ -5,4 +5,15 @@
#define HPET_BASE_ADDRESS 0xfed00000
+/**
+ * Definitions are from IA-PC HPET (High Precision Event Timers) Specification,
+ * Revision 1.0a
+ */
+#define HPET_GEN_CAP_ID 0x0
+#define HPET_NUM_TIM_CAP_MASK 0x1f
+#define HPET_NUM_TIM_CAP_SHIFT 8
+
+#define HPET_TMR0_CNF_CAP 0x100
+#define HPET_TIMER_FSB_EN_CNF_MASK (1 << 15)
+
#endif /* ARCH_X86_HPET_H */