diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-07-03 17:04:21 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-07 20:07:27 +0200 |
| commit | 1936f6cf25bee5a0eb313d6734df7af871757e7c (patch) | |
| tree | 41bfb289d9ee27700bbbeaf46dca5ab899708576 /src/arch | |
| parent | d17a8623a54f40c3a8e0aab35859d8e18e73e4a0 (diff) | |
timestamp: add generic cache region
In order to accommodate tracking timestamps in all the
__PRE_RAM__ stages (bootblock, verstage, romstage, etc)
of a platform one needs to provide a way to specify
a persistent region of SRAM or cache-as-ram to store
the timestamps until cbmem comes online. Provide that
infrastructure.
Based on original patches from chromium.org:
Original-Change-Id: I4d78653c0595523eeeb02115423e7fecceea5e1e
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/223348
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Change-Id: Ie5ffda3112d626068bd1904afcc5a09bc4916d16
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/224024
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Change-Id: I8779526136e89ae61a6f177ce5c74a6530469ae1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10790
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch')
| -rw-r--r-- | src/arch/x86/init/romstage.ld | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 7b9cb6aa45..951ca656a3 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -52,6 +52,11 @@ SECTIONS . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { _car_data_start = .; +#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) + _timestamp = .; + . = . + 0x100; + _etimestamp = .; +#endif *(.car.global_data); _car_data_end = .; /* The preram cbmem console area comes last to take advantage |