symbols.h: Add macro to define memlayout region symbols

When <symbols.h> was first introduced, it only declared a handful of
regions and we didn't expect that too many architectures and platforms
would need to add their own later. However, our amount of platforms has
greatly expanded since, and with them the need for more special memory
regions. The amount of code duplication is starting to get unsightly,
and platforms keep defining their own <soc/symbols.h> files that need
this as well.

This patch adds another macro to cut down the definition boilerplate.
Unfortunately, macros cannot define other macros when they're called, so
referring to region sizes as _name_size doesn't work anymore. This patch
replaces the scheme with REGION_SIZE(name).

Not touching the regions in the x86-specific <arch/symbols.h> yet since
they don't follow the standard _region/_eregion naming scheme. They can
be converted later if desired.

Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 13 insertions, 9 deletions

diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c
index 682c2bc39e..7f8e2a03f0 100644
--- a/src/arch/arm/tables.c
+++ b/src/arch/arm/tables.c
@@ -28,14 +28,14 @@ void bootmem_arch_add_ranges(void)
 {
 	DECLARE_OPTIONAL_REGION(ttb_subtables);
 
-	bootmem_add_range((uintptr_t)_ttb, _ttb_size, BM_MEM_RAMSTAGE);
-	bootmem_add_range((uintptr_t)_ttb_subtables, _ttb_subtables_size,
+	bootmem_add_range((uintptr_t)_ttb, REGION_SIZE(ttb), BM_MEM_RAMSTAGE);
+	bootmem_add_range((uintptr_t)_ttb_subtables, REGION_SIZE(ttb_subtables),
 			  BM_MEM_RAMSTAGE);
 
 	if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER))
 		return;
 	bootmem_add_range((uintptr_t)_postram_cbfs_cache,
-			  _postram_cbfs_cache_size, BM_MEM_RAMSTAGE);
+			  REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE);
 }
 
 void lb_arch_add_records(struct lb_header *header)
diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c
index ec949fd83b..b0010c4b9e 100644
--- a/src/arch/arm64/tables.c
+++ b/src/arch/arm64/tables.c
@@ -28,15 +28,17 @@ void arch_write_tables(uintptr_t coreboot_table)
 
 void bootmem_arch_add_ranges(void)
 {
-	bootmem_add_range((uintptr_t)_ttb, _ttb_size, BM_MEM_RAMSTAGE);
+	bootmem_add_range((uintptr_t)_ttb, REGION_SIZE(ttb), BM_MEM_RAMSTAGE);
 
-	if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) && _bl31_size > 0)
-		bootmem_add_range((uintptr_t)_bl31, _bl31_size, BM_MEM_BL31);
+	if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) &&
+	    REGION_SIZE(bl31) > 0)
+		bootmem_add_range((uintptr_t)_bl31, REGION_SIZE(bl31),
+				  BM_MEM_BL31);
 
 	if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER))
 		return;
 	bootmem_add_range((uintptr_t)_postram_cbfs_cache,
-			  _postram_cbfs_cache_size, BM_MEM_RAMSTAGE);
+			  REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE);
 }
 
 void lb_arch_add_records(struct lb_header *header)
diff --git a/src/arch/mips/cache.c b/src/arch/mips/cache.c
index e17075c081..62c20f34a3 100644
--- a/src/arch/mips/cache.c
+++ b/src/arch/mips/cache.c
@@ -111,5 +111,6 @@ void arch_segment_loaded(uintptr_t start, size_t size, int flags)
 {
 	cache_invalidate_all(start, size);
 	if (flags & SEG_FINAL)
-		cache_invalidate_all((uintptr_t)_cbfs_cache, _cbfs_cache_size);
+		cache_invalidate_all((uintptr_t)_cbfs_cache,
+				     REGION_SIZE(cbfs_cache));
 }
diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
index b5a94982a6..e455b45612 100644
--- a/src/arch/x86/acpi_s3.c
+++ b/src/arch/x86/acpi_s3.c
@@ -172,7 +172,8 @@ void acpi_prepare_resume_backup(void)
 	if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE))
 		return;
 
-	backup_create_or_update(NULL, (uintptr_t)_program, _program_size);
+	backup_create_or_update(NULL, (uintptr_t)_program,
+				REGION_SIZE(program));
 }
 
 #define WAKEUP_BASE 0x600