diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-04-11 16:34:44 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-04-17 15:05:08 +0000 |
| commit | 0a9be33a8aa8e41663c58e0f2f1641f44c7cf5de (patch) | |
| tree | 93e9081bee530feb4b7801f10682fb0dcaa9f257 /src/arch/x86/include | |
| parent | 26c43b7a77bdf28680ef663ef6eb61f6bf8252ab (diff) | |
soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15
This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to
calculate nominal TSC frequency.
As per SDM recommendation:
For any processor in which CPUID.15H is enumerated and
MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is
available, a more accurate frequency can be obtained by using CPUID.15H
This patch also adds header file to capture Intel processor model number.
BUG=b:129839774
TEST=Boot ICL platform and calculate TSC frequency using below methods
1. TSC freq calculated based on MSR 0xCE
tsc: Detected 1600.000 MHz processor
2. TSC freq calculated based on CPUID 0x15
tsc: Detected 1612.800 MHz TSC
Method 2 actually reduce ~25ms of boot performance time.
Note: Method 2 is recommended from gen 6 processor onwards.
Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src/arch/x86/include')
| -rw-r--r-- | src/arch/x86/include/arch/intel-family.h | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/src/arch/x86/include/arch/intel-family.h b/src/arch/x86/include/arch/intel-family.h new file mode 100644 index 0000000000..43eb0e6b34 --- /dev/null +++ b/src/arch/x86/include/arch/intel-family.h @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ARCH_INTEL_FAMILY_H +#define ARCH_INTEL_FAMILY_H + +#define CPU_MODEL_INTEL_CORE_YONAH 0x0E + +#define CPU_MODEL_INTEL_CORE2_MEROM 0x0F +#define CPU_MODEL_INTEL_CORE2_MEROM_L 0x16 +#define CPU_MODEL_INTEL_CORE2_PENRYN 0x17 +#define CPU_MODEL_INTEL_CORE2_DUNNINGTON 0x1D + +#define CPU_MODEL_INTEL_NEHALEM 0x1E +/* Auburndale / Havendale */ +#define CPU_MODEL_INTEL_NEHALEM_G 0x1F +#define CPU_MODEL_INTEL_NEHALEM_EP 0x1A +#define CPU_MODEL_INTEL_NEHALEM_EX 0x2E + +#define CPU_MODEL_INTEL_WESTMERE 0x25 +#define CPU_MODEL_INTEL_WESTMERE_EP 0x2C +#define CPU_MODEL_INTEL_WESTMERE_EX 0x2F + +#define CPU_MODEL_INTEL_SANDYBRIDGE 0x2A +#define CPU_MODEL_INTEL_SANDYBRIDGE_X 0x2D +#define CPU_MODEL_INTEL_IVYBRIDGE 0x3A +#define CPU_MODEL_INTEL_IVYBRIDGE_X 0x3E + +#define CPU_MODEL_INTEL_HASWELL_CORE 0x3C +#define CPU_MODEL_INTEL_HASWELL_X 0x3F +#define CPU_MODEL_INTEL_HASWELL_ULT 0x45 +#define CPU_MODEL_INTEL_HASWELL_GT3E 0x46 + +#define CPU_MODEL_INTEL_BROADWELL_CORE 0x3D +#define CPU_MODEL_INTEL_BROADWELL_GT3E 0x47 +#define CPU_MODEL_INTEL_BROADWELL_X 0x4F +#define CPU_MODEL_INTEL_BROADWELL_XEON_D 0x56 + +#define CPU_MODEL_INTEL_SKYLAKE_MOBILE 0x4E +#define CPU_MODEL_INTEL_SKYLAKE_DESKTOP 0x5E +#define CPU_MODEL_INTEL_SKYLAKE_X 0x55 +#define CPU_MODEL_INTEL_KABYLAKE_MOBILE 0x8E +#define CPU_MODEL_INTEL_KABYLAKE_DESKTOP 0x9E +#define CPU_MODEL_INTEL_CANNONLAKE_MOBILE 0x66 +#define CPU_MODEL_INTEL_ICELAKE_MOBILE 0x7E + +/* "Small Core" Processors (Atom) */ + +#define CPU_MODEL_INTEL_ATOM_PINEVIEW 0x1C +#define CPU_MODEL_INTEL_ATOM_LINCROFT 0x26 +#define CPU_MODEL_INTEL_ATOM_PENWELL 0x27 +#define CPU_MODEL_INTEL_ATOM_CLOVERVIEW 0x35 +#define CPU_MODEL_INTEL_ATOM_CEDARVIEW 0x36 +/* BayTrail/BYT / Valleyview */ +#define CPU_MODEL_INTEL_ATOM_SILVERMONT1 0x37 +/* Avaton/Rangely */ +#define CPU_MODEL_INTEL_ATOM_SILVERMONT2 0x4D +/* CherryTrail / Braswell */ +#define CPU_MODEL_INTEL_ATOM_AIRMONT 0x4C +/* Tangier */ +#define CPU_MODEL_INTEL_ATOM_MERRIFIELD 0x4A +/* Anniedale */ +#define CPU_MODEL_INTEL_ATOM_MOOREFIELD 0x5A +#define CPU_MODEL_INTEL_ATOM_GOLDMONT 0x5C +/* Goldmont Microserver */ +#define CPU_MODEL_INTEL_ATOM_DENVERTON 0x5F +#define CPU_MODEL_INTEL_ATOM_GEMINI_LAKE 0x7A + +/* Xeon Phi */ + +/* Knights Landing */ +#define CPU_MODEL_INTEL_XEON_PHI_KNL 0x57 +/* Knights Mill */ +#define CPU_MODEL_INTEL_XEON_PHI_KNM 0x85 + +#endif /* ARCH_INTEL_FAMILY_H */ |