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authorAamir Bohra <aamir.bohra@intel.com>2019-07-26 10:38:17 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-07-31 09:10:40 +0000
commitcac5e9472622f43c0b33d70f20adef801b345773 (patch)
tree124e55c93fca9601c3d80cfb78269a24b61fed4c /src/arch/x86/boot.c
parent28883db36f21cdf7cf1b83737d37484057d8d10c (diff)
soc/intel/common/block/lpss: Correct the PCI device reference
The initial implementation was assigning the devfn as PCI device reference directly which was incorrect. Change-Id: Iad57e9bc6b2acf1823ee38116aea8a93feece6f9 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/arch/x86/boot.c')
0 files changed, 0 insertions, 0 deletions