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author | Felix Held <felix-coreboot@felixheld.de> | 2024-01-17 22:00:13 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-01 11:36:05 +0000 |
commit | 5881f8ae3658bf3a4d5bf13a6b9c4c092c08a997 (patch) | |
tree | 569e79c038f543f9e483a7d312787acfa940cc19 /src/arch/riscv | |
parent | 8cfb4dc489ad30476b4c6ae57636e7a1e25398b0 (diff) |
soc/amd/common,genoa_poc/domain: rework check for 1st domain
Previously the code checked if the first downstream bus of the domain
was bus 0 in segment group 0 to only run certain code for the first
domain. Instead check if the domain number is 0 which should make the
code a bit easier to understand.
TEST=add_opensil_memmap still gets called exactly once on Onyx
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id8cc0078843e5e0361a53ba897cde508cee16aad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions