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| author | Saurabh Satija <saurabh.satija@intel.com> | 2016-05-03 15:15:31 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-02 03:33:52 +0200 |
| commit | e46dbcc53a10491f53a0c80c4e3c59404982b42d (patch) | |
| tree | a2ef0b396647fc93a65258bba015fa552e48c603 /src/arch/riscv | |
| parent | 5b6c5a500ed416f033a22eed1d8174063ebaf143 (diff) | |
soc/apollolake: Allow enable/disable of LPSS S0ix from devicetree
Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15055
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions