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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2024-03-21 08:05:03 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-03-23 18:05:34 +0000 |
| commit | cb92d28d7a22811f5399c589e5b231508ff42370 (patch) | |
| tree | 6d2915cf77ddf5d1b2b11e040023e1f378a7954f /src/arch/riscv/trap_util.S | |
| parent | 2b24fc7c56da2fe23a3a94def166ff2872d058d5 (diff) | |
soc/intel/xeon_sp/spr: Move XHCI code into southbridge folder
Move the XHCI code into soc/intel/xeon_sp/ebg where it belongs.
TEST=intel/archercity CRB
Change-Id: I2206ec5426a0f922cfce0e2d968e6806d349a6b2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Diffstat (limited to 'src/arch/riscv/trap_util.S')
0 files changed, 0 insertions, 0 deletions