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| author | Johnny Lin <johnny_lin@wiwynn.com> | 2020-04-20 18:56:52 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-02 07:45:54 +0000 |
| commit | 2fc0b1c0184fa74acd7c1003f717039bc4b1457e (patch) | |
| tree | 66bbcd113ad6b8069d8e2dad51e3eb14a4f88128 /src/arch/riscv/opensbi.c | |
| parent | f01a7696f6f17de182ef6153f5dca4893d084910 (diff) | |
soc/xeon_sp/skx: Define MSR PPIN related registers
These changes are in accordance with the documentation:
[*] page 208-209
Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
Volume 4: Model-Specific Registers. May 2019.
Order Number: 335592-070US
Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I5e1de8bcb651fb8ae8b106db1978235b0dd84c47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40523
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/riscv/opensbi.c')
0 files changed, 0 insertions, 0 deletions