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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2018-02-16 13:36:47 +0100
committerMartin Roth <martinroth@google.com>2018-02-20 20:46:12 +0000
commit042a8336f3eb7c7ed4358a100fae23967346e7a2 (patch)
tree50751f64e4352cc518b02b6ce9a9c1a388c23f58 /src/arch/riscv/include
parentb26759d703b636d1462d31cfa38fd3b3d8c90bfe (diff)
arch/riscv: Pass the bootrom-provided FDT to the payload
The RISC-V boot protocol foresees that at every stage boundary (bootrom to boot loader, boot loader -> OS), register a0 contains the Hart ID and a1 contains the physical address of the Flattened Device Tree that the stage shall use. As a first step, pass the bootrom-provided FDT to the payload, unmodified. Change-Id: I468bc64a47153d564087235f1c7e2d10e3d7a658 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/include')
-rw-r--r--src/arch/riscv/include/arch/boot.h21
1 files changed, 21 insertions, 0 deletions
diff --git a/src/arch/riscv/include/arch/boot.h b/src/arch/riscv/include/arch/boot.h
new file mode 100644
index 0000000000..24c1bedebf
--- /dev/null
+++ b/src/arch/riscv/include/arch/boot.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Jonathan Neuschäfer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ARCH_RISCV_INCLUDE_ARCH_BOOT_H
+#define ARCH_RISCV_INCLUDE_ARCH_BOOT_H
+
+extern const void *rom_fdt;
+
+#endif