diff options
| author | Julius Werner <jwerner@chromium.org> | 2018-08-02 17:42:29 -0700 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2018-08-07 20:55:58 +0000 |
| commit | 94e2ec72531c9a0d99081381f3ce3a82a6754af3 (patch) | |
| tree | 1bfb7d154b9ffd3e00deea224d8f76f87ccc73b8 /src/arch/arm64 | |
| parent | b47b6e9f2808ab3f6c8eb83e363d99e846f498b9 (diff) | |
arch: Retire cache_sync_instructions() from <arch/cache.h> (except arm)
cache_sync_instructions() has been superseded by
arch_program_segment_loaded() and friends for a while. There are no uses
in common code anymore, so let's remove it from <arch/cache.h> for all
architectures.
arm64 still has an implementation and one reference, but they are not
really needed since arch_program_segment_loaded() does the same thing
already. Remove them.
Leave it in arm(32) since there are several references (including in SoC
code) that I don't feel like tracking down and testing right now.
Change-Id: I6b776ad49782d981d6f1ef0a0e013812cf408524
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/arm64')
| -rw-r--r-- | src/arch/arm64/armv8/cache.c | 10 | ||||
| -rw-r--r-- | src/arch/arm64/boot.c | 2 | ||||
| -rw-r--r-- | src/arch/arm64/include/armv8/arch/cache.h | 3 |
3 files changed, 0 insertions, 15 deletions
diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index 53aefe0bc4..59d56b2902 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -118,16 +118,6 @@ void dcache_invalidate_by_mva(void const *addr, size_t len) dcache_op_va(addr, len, OP_DCIVAC); } -void cache_sync_instructions(void) -{ - uint32_t sctlr = raw_read_sctlr_current(); - if (sctlr & SCTLR_C) - dcache_clean_all(); /* includes trailing DSB (assembly) */ - else if (sctlr & SCTLR_I) - dcache_clean_invalidate_all(); - icache_invalidate_all(); /* includdes leading DSB and trailing ISB. */ -} - /* * For each segment of a program loaded this function is called * to invalidate caches for the addresses of the loaded segment diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 3804515392..5fd46a7ebd 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -39,8 +39,6 @@ static void run_payload(struct prog *prog) else { uint8_t current_el = get_current_el(); - cache_sync_instructions(); - printk(BIOS_SPEW, "entry = %p\n", doit); /* If current EL is not EL3, jump to payload at same EL. */ diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 8e133efcff..7bf81cf258 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -76,9 +76,6 @@ void dcache_clean_invalidate_all(void); /* returns number of bytes per cache line */ unsigned int dcache_line_bytes(void); -/* perform all icache/dcache maintenance needed after loading new code */ -void cache_sync_instructions(void); - /* tlb invalidate all */ void tlb_invalidate_all(void); |