diff options
| author | Julius Werner <jwerner@chromium.org> | 2015-05-13 11:19:33 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-05-19 20:35:10 +0200 |
| commit | da3a146caea1e85c9651a7f5889ad2a547d6f5e7 (patch) | |
| tree | 186a8d3d727aed1c7bb601f90b487c4383ff4313 /src/arch/arm64/include/armv8 | |
| parent | 745a75faac970ec5dd35472412ddb94e888e4198 (diff) | |
arm64: Make SPSR exception masking on EL2 transition explicit
The configuration of SPSR bits that mask processor exceptions is kinda
oddly hidden as an implict part of the transition() function right now.
It would be odd but not impossible for programs to want to be entered
with enabled exceptions, so let's move these bits to be explicitly set
by the caller like the rest of SPSR instead.
Also clear up some macro names. The SPSR[I] bit is currently defined as
SPSR_IRQ_ENABLE, which is particularly unfortunate since that bit
actually *disables* (masks) interrupts. The fact that there is an
additional SPSR_IRQ_MASK definition with the same value but a different
purpose doesn't really help. There's rarely a point to have all three of
xxx_SHIFT, xxx_MASK and xxx_VALUE macros for single-bit fields, so
simplify this to a single definition per bit. (Other macros in
lib_helpers.h should probably also be overhauled to conform, but I want
to wait and see how many of them really stay relevant after upcoming
changes first.)
BRANCH=None
BUG=None
TEST=None
Change-Id: Id126f70d365467e43b7f493c341542247e5026d2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 715600c83aef9794d1674e8c3b62469bdc57f297
Original-Change-Id: I3edc4ee276feb8610a636ec7b4175706505d58bd
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/270785
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10250
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/arm64/include/armv8')
| -rw-r--r-- | src/arch/arm64/include/armv8/arch/lib_helpers.h | 17 |
1 files changed, 5 insertions, 12 deletions
diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h index 315a0c0b03..55eff27458 100644 --- a/src/arch/arm64/include/armv8/arch/lib_helpers.h +++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h @@ -39,18 +39,11 @@ #define SPSR_M_SHIFT 4 #define SPSR_ERET_32 (1 << SPSR_M_SHIFT) #define SPSR_ERET_64 (0 << SPSR_M_SHIFT) -#define SPSR_FIQ_SHIFT 6 -#define SPSR_FIQ_MASK (0 << SPSR_FIQ_SHIFT) -#define SPSR_FIQ_ENABLE (1 << SPSR_FIQ_SHIFT) -#define SPSR_IRQ_SHIFT 7 -#define SPSR_IRQ_MASK (0 << SPSR_IRQ_SHIFT) -#define SPSR_IRQ_ENABLE (1 << SPSR_IRQ_SHIFT) -#define SPSR_SERROR_SHIFT 8 -#define SPSR_SERROR_MASK (0 << SPSR_SERROR_SHIFT) -#define SPSR_SERROR_ENABLE (1 << SPSR_SERROR_SHIFT) -#define SPSR_DEBUG_SHIFT 9 -#define SPSR_DEBUG_MASK (0 << SPSR_DEBUG_SHIFT) -#define SPSR_DEBUG_ENABLE (1 << SPSR_DEBUG_SHIFT) +#define SPSR_FIQ (1 << 6) +#define SPSR_IRQ (1 << 7) +#define SPSR_SERROR (1 << 8) +#define SPSR_DEBUG (1 << 9) +#define SPSR_EXCEPTION_MASK (SPSR_FIQ | SPSR_IRQ | SPSR_SERROR | SPSR_DEBUG) #define SCR_NS_SHIFT 0 #define SCR_NS_MASK (1 << SCR_NS_SHIFT) |