diff options
| author | Jimmy Huang <jimmy.huang@mediatek.com> | 2015-04-01 18:27:12 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-22 09:01:40 +0200 |
| commit | 6e41523e70b40c92b05c4d52a2b0ddb276e76921 (patch) | |
| tree | 1693bf0a0700ae77fc06c544bb2ec180926c4df9 /src/arch/arm64/include/armv8 | |
| parent | 5d302c75d84ee71f1e4b7b36a7d67f96b74ee096 (diff) | |
arm64: save and restore cntfrq for secondary cpus
CNTFRQ_EL0 can only be set in highest implemented exception level.
Save and restore CNTFRQ_EL0 for secondary cpus in coreboot.
This patch fix the error below:
SANITY CHECK: Unexpected variation in cntfrq. Boot CPU:
0x00000000c65d40, CPU1: 0x00000000000000
BRANCH=none
BUG=none
TEST=boot to kernel on oak board and check secondary cpu's cntfrq.
confirmed cpu1's cntfrq is same as boot cpu's.
Change-Id: I9fbc3c82c2544f0b59ec34b1d631dadf4b9d40eb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b47e4e649efc7f79f016522c7d8a240f98225598
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Change-Id: I2d71b0ccfe42e8a30cd1367d10b0f8993431ef8c
Original-Reviewed-on: https://chromium-review.googlesource.com/264914
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9921
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/arm64/include/armv8')
| -rw-r--r-- | src/arch/arm64/include/armv8/arch/lib_helpers.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h index 1e04d48cfa..bb7300f2b7 100644 --- a/src/arch/arm64/include/armv8/arch/lib_helpers.h +++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h @@ -261,6 +261,16 @@ 402: .endm +/* Macro to read from an el0 register */ +.macro read_el0 xreg sysreg + mrs \xreg, \sysreg\()_el0 +.endm + +/* Macro to write to an el0 register */ +.macro write_el0 sysreg xreg temp + msr \sysreg\()_el0, \xreg +.endm + /* Macro to invalidate all stage 1 TLB entries for current EL */ .macro tlbiall_current temp switch_el \temp, 401f, 402f, 403f @@ -547,6 +557,8 @@ uint64_t raw_read_vbar_current(void); void raw_write_vbar_current(uint64_t vbar); uint64_t raw_read_vbar(uint32_t el); void raw_write_vbar(uint64_t vbar, uint32_t el); +uint32_t raw_read_cntfrq_el0(void); +void raw_write_cntfrq_el0(uint32_t cntfrq_el0); /* Cache maintenance system instructions */ void dccisw(uint64_t cisw); |