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authorHarsha B R <harsha.b.r@intel.com>2023-02-04 12:56:01 +0530
committerSridhar Siricilla <sridhar.siricilla@intel.com>2023-02-08 04:56:47 +0000
commit58973822698005287d0b51102d6d55398d8fdcb9 (patch)
tree0056039f3854c3e6316ded3e2ae1a90924e137cf /spd
parent4aa7d2d5ac7bc1e8f20cd36eb54af63d5b94c6c3 (diff)
mb/intel/mtlrvp: Describe TCSS USB ports
This patch describes the TCSS USB ports for mtlrvp as per schematics. This patch describes TCSS ports for UPC_TYPE_C_USB2_SS_SWITCH as below, tcss_usb3_port1: USB3 Type-C Port C0 tcss_usb3_port2: USB3 Type-C Port C1 tcss_usb3_port3: USB3 Type-C Port C2 tcss_usb3_port4: USB3 Type-C Port C3 BUG=b:224325352 BRANCH=None TEST=Able to build and boot MTLRVP to ChromeOS. Verify the enumeration of xhci (0d.0) as part of lspci. Also verify the enumeration of Type-C ports as part of cbmem -c. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I0054ac4e3d1d9b97cfea615831ec8f3d3e00c9e0 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72785 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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