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authorCaveh Jalali <caveh@chromium.org>2020-07-24 21:57:10 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-08-03 05:06:34 +0000
commit7eaac6cdc1056bb99b92fc8618ae26af8d5ec111 (patch)
treecfe4e1aee90c4a30031dc5cbfeb5efa1925be804 /payloads
parent6d9f24383539bcd2d24a31054a41977e5d004c5e (diff)
soc/intel/tigerlake: Invoke PCIe root port swapping
PCIe bus:function specifiers need to be coalesced the same way functions are coalesced during bus enumeration. Invoke PCIe root port devicetree update to swap the enabled root port devices with the disabled devices. At this point, the TGL pci_devs.h only describes the PCH-LP, so only the PCH-LP root ports are listed in this patch. We'll need to add additional PCIe root ports when PCH-H support is added. BUG=b:162106164 TEST=Ensure that the PCIe device 1c.7 corresponding to Root port 8 is swapped with the PCIe device 1c.0 corresponding to Root port 1. Change-Id: I9230de8b1818f3f2115dab923841fd0e7778be62 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'payloads')
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