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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2020-12-05 16:49:43 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-02-05 09:39:58 +0000
commit5b302b2ed213b8cfbeb901aaed650bf73c3742fc (patch)
tree58f9446c2fe2ea890e658454bb61e18f27376042 /payloads/libpayload
parent6fb87c2b7705f8266a4468740c31c1a372c9da88 (diff)
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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