diff options
author | Subrata Banik <subratabanik@google.com> | 2022-03-31 00:16:00 +0530 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-02 15:00:55 +0000 |
commit | def18c4068cf1d07cc67f71d62e0ac5bc7e84afa (patch) | |
tree | 068746a791a4ca7a58bccd42dd70b0ad79cad0df /payloads/libpayload/libcbfs | |
parent | 1f09a2ac81fe4e0b9401cad8e39df18382424373 (diff) |
soc/intel/common/block/fast_spi: Refactor ROM caching implementation
This patch removes different implementation to cache the SPI ROM between
early and later boot stage where SPI ROM caching doesn't need even
advanced implementation like `mtrr_use_temp_range()` as SPI ROM ranage
is always mapped to below 4GB hence, simple `set_var_mtrr()` function
can be sufficient without any additional complexity.
BUG=b:225766934
TEST=Calling into `fast_spi_cache_bios_region()` from ramstage is able
to update the temporary variable range MTRRs and showed ~44ms of boot
time savings as below:
Before:
90:starting to load payload 1,084,052 (14)
15:starting LZMA decompress (ignore for x86) 1,084,121 (68)
16:finished LZMA decompress (ignore for x86) 1,140,742 (56,620)
After:
90:starting to load payload 1,090,433 (14)
15:starting LZMA decompress (ignore for x86) 1,090,650 (217)
16:finished LZMA decompress (ignore for x86) 1,102,896 (12,245)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I43973b45dc6d032cfcc920eeb36b37fe027e6e8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63221
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'payloads/libpayload/libcbfs')
0 files changed, 0 insertions, 0 deletions