diff options
| author | Jianjun Wang <jianjun.wang@mediatek.com> | 2021-07-28 16:44:43 +0800 |
|---|---|---|
| committer | Yu-Ping Wu <yupingso@google.com> | 2022-05-20 02:51:33 +0000 |
| commit | 2ad74deb2a11772cdd23c3613b58e9116b36863a (patch) | |
| tree | 2227c58f32498b55cfa49833225ccd837d35375e /payloads/libpayload/include | |
| parent | 7439a49f4c306efe22c6c79babf42f2ca473d567 (diff) | |
libpayload/pci: Add support for bus mapping
Move the common APIs to pci_ops.c and IO based operations to
pci_io_ops.c, and add pci_map_bus_ops.c to support bus mapping.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'payloads/libpayload/include')
| -rw-r--r-- | payloads/libpayload/include/pci.h | 16 |
1 files changed, 10 insertions, 6 deletions
diff --git a/payloads/libpayload/include/pci.h b/payloads/libpayload/include/pci.h index ce5081c48b..d78b8cab5e 100644 --- a/payloads/libpayload/include/pci.h +++ b/payloads/libpayload/include/pci.h @@ -31,6 +31,8 @@ #define _PCI_H #include <arch/types.h> +#include <stdint.h> + typedef u32 pcidev_t; /* Device config space registers. */ @@ -100,13 +102,15 @@ typedef u32 pcidev_t; #define PCI_SLOT(_d) ((_d >> 11) & 0x1f) #define PCI_FUNC(_d) ((_d >> 8) & 0x7) -u8 pci_read_config8(u32 device, u16 reg); -u16 pci_read_config16(u32 device, u16 reg); -u32 pci_read_config32(u32 device, u16 reg); +uintptr_t pci_map_bus(pcidev_t dev); + +u8 pci_read_config8(pcidev_t dev, u16 reg); +u16 pci_read_config16(pcidev_t dev, u16 reg); +u32 pci_read_config32(pcidev_t dev, u16 reg); -void pci_write_config8(u32 device, u16 reg, u8 val); -void pci_write_config16(u32 device, u16 reg, u16 val); -void pci_write_config32(u32 device, u16 reg, u32 val); +void pci_write_config8(pcidev_t dev, u16 reg, u8 val); +void pci_write_config16(pcidev_t dev, u16 reg, u16 val); +void pci_write_config32(pcidev_t dev, u16 reg, u32 val); int pci_find_device(u16 vid, u16 did, pcidev_t *dev); u32 pci_read_resource(pcidev_t dev, int bar); |