diff options
author | Subrata Banik <subratabanik@google.com> | 2024-05-18 12:26:40 +0000 |
---|---|---|
committer | Subrata Banik <subratabanik@google.com> | 2024-05-26 01:26:31 +0000 |
commit | afa39105d8e09e5bc9ce2053b10a40839ab9fddd (patch) | |
tree | f91dd504481261abae734b52eb12c6c46028a925 /payloads/libpayload/include/x86 | |
parent | 4244527d8ccf2256c567ec4c4091c5edad72d06c (diff) |
libpayload: Add x86_64 (64-bit) support
This patch introduces x86_64 (64-bit) support to the payload, building
upon the existing x86 (32-bit) architecture. Files necessary for 64-bit
compilation are now guarded by the `CONFIG_LP_ARCH_X86_64` Kconfig
option.
BUG=b:242829490
TEST=Able to verify all valid combinations between coreboot and
payload with this patch.
Payload Entry Point Behavior with below code.
+----------------+--------------------+----------------------------+
| LP_ARCH_X86_64 | Payload Entry Mode | Description |
+----------------+--------------------+----------------------------+
| No | 32-bit | Direct protected mode init |
+----------------+--------------------+----------------------------+
| Yes | 32-bit | Protected to long mode |
+----------------+--------------------+----------------------------+
| Yes | 64-bit | Long mode initialization |
+----------------+--------------------+----------------------------+
Change-Id: I69fda47bedf1a14807b1515c4aed6e3a1d5b8585
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81968
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'payloads/libpayload/include/x86')
-rw-r--r-- | payloads/libpayload/include/x86/arch/exception.h | 67 |
1 files changed, 51 insertions, 16 deletions
diff --git a/payloads/libpayload/include/x86/arch/exception.h b/payloads/libpayload/include/x86/arch/exception.h index d88029b39e..76099f2b71 100644 --- a/payloads/libpayload/include/x86/arch/exception.h +++ b/payloads/libpayload/include/x86/arch/exception.h @@ -29,6 +29,7 @@ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H +#include <stddef.h> #include <stdint.h> void exception_init_asm(void); @@ -38,20 +39,28 @@ void disable_interrupts(void); /** Returns 1 if interrupts are enabled. */ int interrupts_enabled(void); -struct exception_state -{ +#if CONFIG(LP_ARCH_X86_64) +struct exception_state { /* Careful: x86/gdb.c currently relies on the size and order of regs. */ struct { - u32 eax; - u32 ecx; - u32 edx; - u32 ebx; - u32 esp; - u32 ebp; - u32 esi; - u32 edi; - u32 eip; - u32 eflags; + size_t reg_ax; + size_t reg_bx; + size_t reg_cx; + size_t reg_dx; + size_t reg_si; + size_t reg_di; + size_t reg_bp; + size_t reg_sp; + size_t reg_r8; + size_t reg_r9; + size_t reg_r10; + size_t reg_r11; + size_t reg_r12; + size_t reg_r13; + size_t reg_r14; + size_t reg_r15; + size_t reg_ip; + size_t reg_flags; u32 cs; u32 ss; u32 ds; @@ -59,13 +68,39 @@ struct exception_state u32 fs; u32 gs; } regs; - u32 error_code; - u32 vector; + size_t error_code; + size_t vector; } __packed; +#else +struct exception_state { + /* Careful: x86/gdb.c currently relies on the size and order of regs. */ + struct { + size_t reg_ax; + size_t reg_cx; + size_t reg_dx; + size_t reg_bx; + size_t reg_sp; + size_t reg_bp; + size_t reg_si; + size_t reg_di; + size_t reg_ip; + size_t reg_flags; + u32 cs; + u32 ss; + u32 ds; + u32 es; + u32 fs; + u32 gs; + } regs; + size_t error_code; + size_t vector; +} __packed; +#endif + extern struct exception_state *exception_state; -extern u32 exception_stack[]; -extern u32 *exception_stack_end; +extern u8 exception_stack[]; +extern u8 *exception_stack_end; enum { EXC_DE = 0, /* Divide by zero */ |