diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2018-03-05 09:53:47 +0100 |
|---|---|---|
| committer | David Hendricks <david.hendricks@gmail.com> | 2018-03-23 04:09:50 +0000 |
| commit | 57afc5e0f2309ba9f7fbd171642f04c6da9d9976 (patch) | |
| tree | aeeafda4fee623141e5a8c162f7612b6454918e7 /payloads/libpayload/arch/arm64 | |
| parent | 3d9462a07f0250cf628b7874620f9f682b7a020e (diff) | |
arch/arm64/armv8/mmu: Add support for 48bit VA
The VA space needs to be extended to support 48bit, as on Cavium SoCs
the MMIO starts at 1 << 47.
The following changes were done to coreboot and libpayload:
* Use page table lvl 0
* Increase VA bits to 48
* Enable 256TB in MMU controller
* Add additional asserts
Tested on Cavium SoC and two ARM64 Chromebooks.
Change-Id: I89e6a4809b6b725c3945bad7fce82b0dfee7c262
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/24970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'payloads/libpayload/arch/arm64')
| -rw-r--r-- | payloads/libpayload/arch/arm64/mmu.c | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index d84f969dc6..c860ee0fc8 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -172,6 +172,7 @@ static uint64_t init_xlat_table(uint64_t base_addr, uint64_t size, uint64_t tag) { + uint64_t l0_index = (base_addr & L0_ADDR_MASK) >> L0_ADDR_SHIFT; uint64_t l1_index = (base_addr & L1_ADDR_MASK) >> L1_ADDR_SHIFT; uint64_t l2_index = (base_addr & L2_ADDR_MASK) >> L2_ADDR_SHIFT; uint64_t l3_index = (base_addr & L3_ADDR_MASK) >> L3_ADDR_SHIFT; @@ -179,12 +180,12 @@ static uint64_t init_xlat_table(uint64_t base_addr, uint64_t desc; uint64_t attr = get_block_attr(tag); - /* L1 table lookup - * If VA has bits more than L2 can resolve, lookup starts at L1 - * Assumption: we don't need L0 table in coreboot */ - if (BITS_PER_VA > L1_ADDR_SHIFT) { - if ((size >= L1_XLAT_SIZE) && - IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) { + /* L0 entry stores a table descriptor (doesn't support blocks) */ + table = get_next_level_table(&table[l0_index], L1_XLAT_SIZE); + + /* L1 table lookup */ + if ((size >= L1_XLAT_SIZE) && + IS_ALIGNED(base_addr, (1UL << L1_ADDR_SHIFT))) { /* If block address is aligned and size is greater than * or equal to size addressed by each L1 entry, we can * directly store a block desc */ @@ -192,13 +193,12 @@ static uint64_t init_xlat_table(uint64_t base_addr, table[l1_index] = desc; /* L2 lookup is not required */ return L1_XLAT_SIZE; - } - table = get_next_level_table(&table[l1_index], L2_XLAT_SIZE); } - /* L2 table lookup - * If lookup was performed at L1, L2 table addr is obtained from L1 desc - * else, lookup starts at ttbr address */ + /* L1 entry stores a table descriptor */ + table = get_next_level_table(&table[l1_index], L2_XLAT_SIZE); + + /* L2 table lookup */ if ((size >= L2_XLAT_SIZE) && IS_ALIGNED(base_addr, (1UL << L2_ADDR_SHIFT))) { /* If block address is aligned and size is greater than @@ -226,6 +226,7 @@ static void sanity_check(uint64_t addr, uint64_t size) { assert(!(addr & GRANULE_SIZE_MASK) && !(size & GRANULE_SIZE_MASK) && + (addr + size < (1UL << BITS_PER_VA)) && size >= GRANULE_SIZE); } @@ -344,7 +345,7 @@ void mmu_enable(void) /* Initialize TCR flags */ raw_write_tcr_current(TCR_TOSZ | TCR_IRGN0_NM_WBWAC | TCR_ORGN0_NM_WBWAC | - TCR_SH0_IS | TCR_TG0_4KB | TCR_PS_64GB | + TCR_SH0_IS | TCR_TG0_4KB | TCR_PS_256TB | TCR_TBI_USED); /* Initialize TTBR */ |