diff options
| author | Raihow Shi <raihow_shi@wistron.corp-partner.google.com> | 2022-07-14 16:26:07 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-07-19 01:49:41 +0000 |
| commit | 44bc4cd5d40db8be7796f1bc52bdab3325941e9b (patch) | |
| tree | 85f460a3e1be5e42e77c1d66543a96599101dd49 /payloads/libpayload/arch/arm/head.S | |
| parent | 50eef6566b223eb2a6c027e9a862bc279bd06ed7 (diff) | |
mb/google/brask/variants/moli: correct USB3 port2 tx_de_emp
Set USB3 port2 tx_de_emp 0x2B by "11th Gen Intel Core Processors for
IoT Platforms EDS Addendum_rev1.6" then fix the USB3 port2 Gen2 RX
failed.
BUG=b:236661824
TEST=emerge-brask coreboot and check USB3 port2 RX pass
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I7a5add20f055a8d871c6b4f33734fb8a397cba76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65848
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'payloads/libpayload/arch/arm/head.S')
0 files changed, 0 insertions, 0 deletions