diff options
author | Nico Huber <nico.huber@secunet.com> | 2018-11-27 15:13:22 +0100 |
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committer | Werner Zeh <werner.zeh@siemens.com> | 2018-12-03 06:10:39 +0000 |
commit | 8885529e15cfa4b01a7678663d2eda9695bb8cfc (patch) | |
tree | 851bfbcbcff4006afe1f37d6b1a059548de512bd /payloads/external | |
parent | aaced4a932dc68268cebace63df079673960c17b (diff) |
soc/intel/apl: Configure LPC serial IRQ mode
Sync the FSP settings with what coreboot does. Why both FSP and coreboot
configure this redundantly stays a secret.
TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC
works correctly now, but was confused by the wrong settings before
because the FSP defaults allowed to disable the LPC clock.
Change-Id: Id1c7180f460678bf0f9458228591050dd628c052
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'payloads/external')
0 files changed, 0 insertions, 0 deletions