mb/intel/mtlrvp: Add romstage and configure LP5 memory parts

This patch adds initial romstage code and spd data for LP5 memory
parts for MTL-RVP. This also configures memory based on the board id.

Memory - x32 LPDDR5
Vendor/Model - Micron/MT62F2G32D8DR-031 WT:B
Board ID -
         0b0000 - Empty spd hex file
         0b0001 - DDR5 (Empty spd hex file)
         0b0010 - LPDDR5 (MT62F2G32D8DR-031 WT:B)

BUG=b:224325352
TEST=Able to boot intel/mtlrvp (LP5 SKU) to ChromeOS

Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Change-Id: I15b352eb246aed23da273e56490c7094eae9d176
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

0 files changed, 0 insertions, 0 deletions