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authorDuncan Laurie <dlaurie@chromium.org>2012-06-23 16:37:45 -0700
committerRonald G. Minnich <rminnich@gmail.com>2012-07-25 00:47:10 +0200
commitf4d362339f4d96657be1dc5956c34278d1089eba (patch)
tree4f07a246238d953f054e8aa3937a65c259529081 /payloads/coreinfo/pci_module.c
parent472ec9cd7ecb3d283bc05941c7dbb54a10813614 (diff)
ELOG: Add support for a monotonic boot counter in CMOS
This maintains a 32bit monotonically increasing boot counter that is stored in CMOS and logged on every non-S3 boot when the event log is initialized. In CMOS the count is prefixed with a 16bit signature and appended with a 16bit checksum. This counter is incremented in sandybridge early_init which is called by romstage. It is incremented early in order notice when reboots happen after memory init. The counter is then logged when ELOG is initialized and will store the boot count as part of a 'System boot; event. Reboot a few times and look for 'System boot' events in the event log and check that they are increasing. Also verify that the counter does NOT increase when resuming from S3. 171 | 2012-06-23 16:02:55 | System boot | 285 176 | 2012-06-23 16:26:00 | System boot | 286 182 | 2012-06-23 16:27:04 | System boot | 287 189 | 2012-06-23 16:31:10 | System boot | 288 Change-Id: I23faeafcf155edfd10aa6882598b3883575f8a33 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1315 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'payloads/coreinfo/pci_module.c')
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