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| author | Jonathan Zhang <jonzhang@meta.com> | 2023-01-25 11:33:16 -0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-19 09:49:03 +0000 |
| commit | 15fc45982b9b8303978ab87ea6c93d423834e6e8 (patch) | |
| tree | e0d4f9203e1cee49ba992f36a20d849362fef06e /configs/config.purism_librem15_v4.txt_build_test | |
| parent | ecb4a24eaa720b4c7be506b0986f7797a3d8dbf6 (diff) | |
soc/intel/xeon_sp/spr: Add header files and romstage code
Several FSP HOBs processing codes are similar to Intel Cooperlake-SP
codes in soc/intel/xeon_sp/cpx.
Register datasheet please reference Sapphire Rapids EDS Vol2 Doc#612246
and Emmitsburg PCH EDS Doc#606161.
Change-Id: Ia022534e5206dbeec946d3e5f3c66bcb5628748f
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'configs/config.purism_librem15_v4.txt_build_test')
0 files changed, 0 insertions, 0 deletions