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| author | Nick Vaccaro <nvaccaro@google.com> | 2021-02-22 14:26:13 -0800 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-02-22 23:20:32 +0000 |
| commit | 202b1899dc0f7701b03a7839bccd3bf0438f1ac7 (patch) | |
| tree | a49e14faa6dfe42bbe417e6ccafb4b3407dfaa9c /configs/config.intel_galileo_gen2.sd | |
| parent | 3e945f1a2333e723a82848bc9f65e833dd03baa8 (diff) | |
soc/intel/tigerlake: Enable end of post support in FSP
Send end of post message to CSME in FSP, by selecting EndOfPost
message in PEI phase. In API mode which coreboot currently uses,
sending EndOfPost message in DXE phase is not applicable.
BUG=b:180755397
TEST=Extract and copy MEInfo tool from CSME Fit Kit to voxel, execute
./MEInfo | grep "BIOS Boot State"
and confirm response shows BIOS Boot State to be "Post Boot".
Change-Id: I1ad0d7cc06e79b2fe1e53d49c8e838f4d91af736
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51012
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'configs/config.intel_galileo_gen2.sd')
0 files changed, 0 insertions, 0 deletions