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authorAaron Durbin <adurbin@chromium.org>2013-10-10 20:54:57 -0500
committerAaron Durbin <adurbin@google.com>2014-02-11 22:22:25 +0100
commit6ecdb68562989aec1362e3a99f3ed2e0012e1191 (patch)
treeb50a259952ad37c1622a73c3807b306ff818657a /Makefile
parentf92271db84d5f3e5fe4765213bfb9d6f1af241fb (diff)
baytrail: add reset support
Bay Trail has the following types of resets it supports: - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92 - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9 - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9 - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9 - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but with ETR[20] set. While these are documented this support currently provides support for 2nd soft reset as well as cold and warm reset. BUG=chrome-os-partner:23249 BRANCH=None TEST=Built and booted. Change-Id: I9746e7c8aed0ffc29e7afa137798e38c5da9c888 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172710 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4878 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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