diff options
| author | Nicholas Chin <nic.c3.14@gmail.com> | 2024-08-18 09:00:46 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-21 16:18:23 +0000 |
| commit | cf2bf984f022ffa57da9ca2eb2f702d4bfb5cea3 (patch) | |
| tree | 161d2998cbe79025d895bd69df334264d25c487f /Documentation | |
| parent | 73be9641002c34a5f5b9052598486ed695bd1059 (diff) | |
Docs: Fix broken header references
MyST Parser automatically generates label "slugs" for headers which
should be used to reference them from links [1]. These labels are in
"slug-case", i.e. the original header text in lower case separated by
dashes, with punctuation removed. This fixes a few "cross-reference
target not found" warnings.
[1] https://myst-parser.readthedocs.io/en/latest/syntax/optional.html#anchor-slug-structure
Change-Id: Ia6970d03b961bde6d7cd0fa3297f8d84b75d3b34
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'Documentation')
4 files changed, 4 insertions, 4 deletions
diff --git a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md index 73d38fe371..a7893e7ad3 100644 --- a/Documentation/mainboard/lenovo/Ivy_Bridge_series.md +++ b/Documentation/mainboard/lenovo/Ivy_Bridge_series.md @@ -82,7 +82,7 @@ It is possible to reduce the Intel ME firmware size to free additional space for the `bios` region. This is usually referred to as *cleaning the ME* or *stripping the ME*. After reducing the Intel ME firmware size you must modify the original IFD, -[split the resulting coreboot ROM](#splitting-the-coreboot-rom) and then write +[split the resulting coreboot ROM](#splitting-the-corebootrom) and then write each ROM using an [external programmer]. Have a look at [me_cleaner] for more information. diff --git a/Documentation/northbridge/intel/sandybridge/nri_freq.md b/Documentation/northbridge/intel/sandybridge/nri_freq.md index 45cac8dfd9..0732870421 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_freq.md +++ b/Documentation/northbridge/intel/sandybridge/nri_freq.md @@ -160,7 +160,7 @@ As you can see, by using DIMMs with different maximum DRAM frequencies, the slowest DIMMs' frequency will be selected, to prevent over-clocking it. The selected frequency gives the PLL multiplier to operate at. In case the PLL -locks (see Take me to [Hard fuses](#hard_fuses)) the frequency will be used for +locks (see Take me to [Hard fuses](#hard-fuses)) the frequency will be used for all DIMMs. At this point it's not possible to change the multiplier again, until the system has been powered off. In case the PLL doesn't lock, the next smaller multiplier will be used until a working multiplier will be found. diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index 600bf67433..29374d1218 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -214,7 +214,7 @@ Deprecations In order to minimize the usage of PCI bus mastering, the options we introduced in this release will be dropped in a future release again. For more details, please -see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering-in-coreboot). +see [Preparations to minimize enabling PCI bus mastering](#preparations-to-minimize-enabling-pci-bus-mastering). ### Resource allocator v3 diff --git a/Documentation/superio/nuvoton/npcd378.md b/Documentation/superio/nuvoton/npcd378.md index 1cc081b740..6e5bf66832 100644 --- a/Documentation/superio/nuvoton/npcd378.md +++ b/Documentation/superio/nuvoton/npcd378.md @@ -78,7 +78,7 @@ Looks like a WDT. ### LDN8 Custom HWM space. It exposes 256 byte of IO config space. -See [HWM](#HWM) for more details. +See [HWM](#hwm) for more details. ## HWM |