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authorAaron Durbin <adurbin@chromium.org>2018-01-26 16:39:04 -0700
committerAaron Durbin <adurbin@chromium.org>2018-01-30 05:38:08 +0000
commit0d2d77a597542354a1fe64cad908f6a9e0d59591 (patch)
treed890fa42eec3b94bea642c9bc718e0ac85be8545 /Documentation
parent063c00c2e00b3457ac336763989a4b254345fb13 (diff)
soc/amd/stoneyridge: use new host controller programming
The SPI controller on stoneyridge apparently has a large fifo and an alternate method for programming the controller. The fifo is directly accessible as well as the rx and tx pointer in addition to the execute bit. Remove the unneeded #defines and program the host controller with the above changes in mind. In addition, add debug hooks to the driver so one can dump the state of the controller when in operation. The time it took to read 4KiB of flash in the elog driver went from 20593 microseconds to 5693 microseconds on cdx03/kahlee. BUG=b:65485690 Change-Id: Ie7ea9d18cef5511686700ad9b2b9fdfeb6d5685b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23493 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation')
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