Docs: Replace Recommonmark with MyST Parser

Recommonmark has been deprecated since 2021 [1] and the last release was
over 3 years ago [2]. As per their announcement, Markedly Structured
Text (MyST) Parser [3] is the recommended replacement.

For the most part, the existing documentation is compatible with MyST,
as both parsers are built around the CommonMark flavor of Markdown. The
main difference that affects coreboot is how the Sphinx toctree is
generated. Recommonmark has a feature called auto_toc_tree, which
converts single level lists of references into a toctree:

* [Part 1: Starting from scratch](part1.md)
* [Part 2: Submitting a patch to coreboot.org](part2.md)
* [Part 3: Writing unit tests](part3.md)
* [Managing local additions](managing_local_additions.md)
* [Flashing firmware](flashing_firmware/index.md)

MyST Parser does not provide a replacement for this feature, meaning the
toctree must be defined manually. This is done using MyST's syntax for
Sphinx directives:

```{toctree}
:maxdepth: 1

Part 1: Starting from scratch <part1.md>
Part 2: Submitting a patch to coreboot.org <part2.md>
Part 3: Writing unit tests <part3.md>
Managing local additions <managing_local_additions.md>
Flashing firmware <flashing_firmware/index.md>
```

Internally, auto_toc_tree essentially converts lists of references into
the Sphinx toctree structure that the MyST syntax above more directly
represents.

The toctrees were converted to the MyST syntax using the following
command and Python script:

`find ./ -iname "*.md" | xargs -n 1 python conv_toctree.py`

```
import re
import sys

in_list = False
f = open(sys.argv[1])
lines = f.readlines()
f.close()

with open(sys.argv[1], "w") as f:
    for line in lines:
        match = re.match(r"^[-*+] \[(.*)\]\((.*)\)$", line)
        if match is not None:
            if not in_list:
                in_list = True
                f.write("```{toctree}\n")
                f.write(":maxdepth: 1\n\n")
            f.write(match.group(1) + " <" + match.group(2) + ">\n")
        else:
            if in_list:
                f.write("```\n")
            f.write(line)
            in_list = False

    if in_list:
        f.write("```\n")
```

While this does add a little more work for creating the toctree, this
does give more control over exactly what goes into the toctree. For
instance, lists of links to external resources currently end up in the
toctree, but we may want to limit it to pages within coreboot.

This change does break rendering and navigation of the documentation in
applications that can render Markdown, such as Okular, Gitiles, or the
GitHub mirror. Assuming the docs are mainly intended to be viewed after
being rendered to doc.coreboot.org, this is probably not an issue in
practice.

Another difference is that MyST natively supports Markdown tables,
whereas with Recommonmark, tables had to be written in embedded rST [4].
However, MyST also supports embedded rST, so the existing tables can be
easily converted as the syntax is nearly identical.

These were converted using
`find ./ -iname "*.md" | xargs -n 1 sed -i "s/eval_rst/{eval-rst}/"`

Makefile.sphinx and conf.py were regenerated from scratch by running
`sphinx-quickstart` using the updated version of Sphinx, which removes a
lot of old commented out boilerplate. Any relevant changes coreboot had
made on top of the previous autogenerated versions of these files were
ported over to the newly generated file.

From some initial testing the generated webpages appear and function
identically to the existing documentation built with Recommonmark.

TEST: `make -C util/docker docker-build-docs` builds the documentation
successfully and the generated output renders properly when viewed in
a web browser.

[1] https://github.com/readthedocs/recommonmark/issues/221
[2] https://pypi.org/project/recommonmark/
[3] https://myst-parser.readthedocs.io/en/latest/
[4] https://doc.coreboot.org/getting_started/writing_documentation.html

Change-Id: I0837c1722fa56d25c9441ea218e943d8f3d9b804
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73158
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

9 files changed, 83 insertions, 27 deletions

diff --git a/Documentation/soc/intel/broadwell/index.md b/Documentation/soc/intel/broadwell/index.md
index 11a3ce1058..0cdd1e7f25 100644
--- a/Documentation/soc/intel/broadwell/index.md
+++ b/Documentation/soc/intel/broadwell/index.md
@@ -4,4 +4,8 @@ This section describes the Intel Broadwell SoC.
 
 ## Proprietary blobs
 
-- [mrc.bin and refcode](blobs.md)
+```{toctree}
+:maxdepth: 1
+
+mrc.bin and refcode <blobs.md>
+```
diff --git a/Documentation/soc/intel/code_development_model/code_development_model.md b/Documentation/soc/intel/code_development_model/code_development_model.md
index 509b8ad3c8..ad27bd498a 100644
--- a/Documentation/soc/intel/code_development_model/code_development_model.md
+++ b/Documentation/soc/intel/code_development_model/code_development_model.md
@@ -58,7 +58,7 @@ the footprint of code as well as have a more unified code flow for all Intel
 SoCs.
 
 Here's a table which summarizes common code phase and status:
-```eval_rst
+```{eval-rst}
 +----------------+---------------------------------------------+--------------+
 |   Common code  |           summary                           |   status     |
 |     phase      |                                             |              |
diff --git a/Documentation/soc/intel/fit.md b/Documentation/soc/intel/fit.md
index 553fef3c16..d2629b4614 100644
--- a/Documentation/soc/intel/fit.md
+++ b/Documentation/soc/intel/fit.md
@@ -17,7 +17,7 @@ The first is called *FIT header* the other are called *FIT entry*.
 Each entry has a *type* that give the other bits in the entry a different
 meaning. The following types are known:
 
-```eval_rst
+```{eval-rst}
 +-----------+------------------------------------------------------------------+
 | no.       | Description                                                      |
 +===========+==================================================================+
@@ -56,5 +56,9 @@ execution of the IA32 reset vector happens.
 
 ## References
 
-* [Intel TXT LAB handout](https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf)
-* [FIT BIOS specification](https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios-specification.pdf)
+```{toctree}
+:maxdepth: 1
+
+Intel TXT LAB handout <https://downloadmirror.intel.com/18931/eng/Intel%20TXT%20LAB%20Handout.pdf>
+FIT BIOS specification <https://www.intel.com/content/dam/www/public/us/en/documents/guides/fit-bios-specification.pdf>
+```
diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md
index feeb5e9433..6d29aca63b 100644
--- a/Documentation/soc/intel/fsp/index.md
+++ b/Documentation/soc/intel/fsp/index.md
@@ -65,23 +65,51 @@ those are fixed. If possible a workaround is described here as well.
 
 ## Open Source Intel FSP specification
 
-* [About Intel FSP](https://firmware.intel.com/learn/fsp/about-intel-fsp)
+```{toctree}
+:maxdepth: 1
 
-* [FSP Specification 1.0](https://www.intel.in/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec.pdf)
+About Intel FSP <https://firmware.intel.com/learn/fsp/about-intel-fsp>
+```
 
-* [FSP Specification 1.1](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf)
+```{toctree}
+:maxdepth: 1
 
-* [FSP Specification 2.0](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf)
+FSP Specification 1.0 <https://www.intel.in/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec.pdf>
+```
 
-* [FSP Specification 2.1](https://cdrdv2.intel.com/v1/dl/getContent/611786)
+```{toctree}
+:maxdepth: 1
+
+FSP Specification 1.1 <https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf>
+```
+
+```{toctree}
+:maxdepth: 1
+
+FSP Specification 2.0 <https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf>
+```
+
+```{toctree}
+:maxdepth: 1
+
+FSP Specification 2.1 <https://cdrdv2.intel.com/v1/dl/getContent/611786>
+```
 
 ## Additional Features in FSP 2.1 specification
 
-- [PPI](ppi/ppi.md)
+```{toctree}
+:maxdepth: 1
+
+PPI <ppi/ppi.md>
+```
 
 ## Official bugtracker
 
-- [IntelFSP/FSP](https://github.com/IntelFsp/FSP/issues)
+```{toctree}
+:maxdepth: 1
+
+IntelFSP/FSP <https://github.com/IntelFsp/FSP/issues>
+```
 
 [Issue 10]: https://github.com/IntelFsp/FSP/issues/10
 [Issue 13]: https://github.com/IntelFsp/FSP/issues/13
diff --git a/Documentation/soc/intel/fsp/ppi/mp_service_ppi.md b/Documentation/soc/intel/fsp/ppi/mp_service_ppi.md
index ab0b5135ed..ce2fb6bbb4 100644
--- a/Documentation/soc/intel/fsp/ppi/mp_service_ppi.md
+++ b/Documentation/soc/intel/fsp/ppi/mp_service_ppi.md
@@ -43,7 +43,7 @@ More details here: [PI_Spec_1_6]
 
 ### coreboot to publish EFI_MP_SERVICES_PPI APIs
 
-```eval_rst
+```{eval-rst}
 +------------------------------+------------------------------------------------------------------+
 | API                          | Description                                                      |
 +==============================+==================================================================+
diff --git a/Documentation/soc/intel/fsp/ppi/ppi.md b/Documentation/soc/intel/fsp/ppi/ppi.md
index 6d7afb47d4..bb14af04e6 100644
--- a/Documentation/soc/intel/fsp/ppi/ppi.md
+++ b/Documentation/soc/intel/fsp/ppi/ppi.md
@@ -6,9 +6,17 @@ chipset using Intel FSP. This feature is added into FSP specification 2.1
 where FSP should be able to locate PPI, published by boot firmware and
 able to execute the same in FSP's context.
 
-* [What is PPI](https://www.intel.com/content/dam/www/public/us/en/documents/reference-guides/efi-pei-cis-v09.pdf)
+```{toctree}
+:maxdepth: 1
+
+What is PPI <https://www.intel.com/content/dam/www/public/us/en/documents/reference-guides/efi-pei-cis-v09.pdf>
+```
 
 ## List of PPI service
 
 ### Publish MP Service PPI from boot firmware (coreboot) to initialize CPU
-- [MP Service PPI](mp_service_ppi.md)
+```{toctree}
+:maxdepth: 1
+
+MP Service PPI <mp_service_ppi.md>
+```
diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md
index 40d0a5603c..5eac084206 100644
--- a/Documentation/soc/intel/index.md
+++ b/Documentation/soc/intel/index.md
@@ -4,12 +4,16 @@ This section contains documentation about coreboot on specific Intel SOCs.
 
 ## Platforms
 
-- [Common code development strategy](code_development_model/code_development_model.md)
-- [FSP](fsp/index.md)
-- [Broadwell](broadwell/index.md)
-- [MP Initialization](mp_init/mp_init.md)
-- [Microcode Updates](microcode.md)
-- [Firmware Interface Table](fit.md)
-- [Apollolake](apollolake/index.md)
-- [CSE FW Update](cse_fw_update/cse_fw_update.md)
-- [Xeon Scalable processor](xeon_sp/index.md)
+```{toctree}
+:maxdepth: 1
+
+Common code development strategy <code_development_model/code_development_model.md>
+FSP <fsp/index.md>
+Broadwell <broadwell/index.md>
+MP Initialization <mp_init/mp_init.md>
+Microcode Updates <microcode.md>
+Firmware Interface Table <fit.md>
+Apollolake <apollolake/index.md>
+CSE FW Update <cse_fw_update/cse_fw_update.md>
+Xeon Scalable processor <xeon_sp/index.md>
+```
diff --git a/Documentation/soc/intel/mp_init/mp_init.md b/Documentation/soc/intel/mp_init/mp_init.md
index f7776e511e..7f21d60df4 100644
--- a/Documentation/soc/intel/mp_init/mp_init.md
+++ b/Documentation/soc/intel/mp_init/mp_init.md
@@ -52,5 +52,9 @@ Typically all platforms supported by FSP 2.1 specification will have
 external PPI service feature implemented.
 
 ## References
-- [PPI](../fsp/ppi/ppi.md)
-- [MP Service PPI](../fsp/ppi/mp_service_ppi.md)
+```{toctree}
+:maxdepth: 1
+
+PPI <../fsp/ppi/ppi.md>
+MP Service PPI <../fsp/ppi/mp_service_ppi.md>
+```
diff --git a/Documentation/soc/intel/xeon_sp/index.md b/Documentation/soc/intel/xeon_sp/index.md
index bab09ca33b..5fe852d66b 100644
--- a/Documentation/soc/intel/xeon_sp/index.md
+++ b/Documentation/soc/intel/xeon_sp/index.md
@@ -5,4 +5,8 @@ processors.
 
 ## Topics
 
-- [Community preview guide](community_preview_guide.md)
+```{toctree}
+:maxdepth: 1
+
+Community preview guide <community_preview_guide.md>
+```