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authorSean Rhodes <sean@starlabs.systems>2022-07-28 20:50:49 +0100
committerMartin Roth <martin.roth@amd.corp-partner.google.com>2022-10-06 18:20:47 +0000
commit291758ddbaa004f9ca2326b3d9f6b5e37bc663ec (patch)
treea5549efecbb09750c70690d4e23b47f9e3cb6da5 /Documentation/releases/coreboot-4.9-relnotes.md
parente72ff319fd14422d5061c2668dcf41d292ac3473 (diff)
soc/intel/apollolake/acpi: Add PCIEXBAR to MCHC
The values in this patch were found in the following datasheets: * 334819 (APL) * 336561 (GLK) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I14c5933b9022703c8951da7c6a26eb703258ec37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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