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| author | Usha P <usha.p@intel.com> | 2020-02-04 11:24:25 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-02-15 04:09:21 +0000 |
| commit | 77eaecf06b238157decfe19fea02eadfa71a9436 (patch) | |
| tree | 6da61dbbd0728bc2305ac0a7d08ba0c1b4fb99fc /Documentation/mainboard_io_trap_handler_sample.c | |
| parent | 611ec48c1db12bad4cbe5bbfde2eb116887971d0 (diff) | |
soc/intel/tigerlake: Update PMC Register Base and platform check for JSP
Change:
1. PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP to 0X0A00 for JSP
2. Platform check in espi.c
BUG=None
TEST=
1. Test for JSL RVP Boot
2. Verify PMC register values are valid for GEN_PMCON
and GBLRST_CAUSE from the coreboot console logs.
Change-Id: I6017a9703764b5454e7be479c1e08afe614908f1
Signed-off-by: Usha P <usha.p@intel.com>
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38704
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/mainboard_io_trap_handler_sample.c')
0 files changed, 0 insertions, 0 deletions