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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2021-05-17 12:25:40 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-18 10:11:45 +0000 |
| commit | f6004114ec3807e15acbc01cee45d4f83254bae2 (patch) | |
| tree | 671259b138aac9df80806a83f9f8468ba21e8631 /Documentation/mainboard/emulation/qemu-riscv.md | |
| parent | 71e797478447e43b9d3be0cae13948a0ea9f0082 (diff) | |
intelblocks/gpio: Add NAVFWE bit to PAD_CFG_DW0 mask definition
Definition for NAV_FWE BIT was added in commit e6e8b3d
Even if try to set this BIT it was not getting set since PAD_CFG_DW0
mask will make it 0 since this bit was not part of mask.
Adding NAV_FWE to mask will resolve this issue and BIT will be set/unset
as per programming in mainboard.
TEST=Check GPIO register dump and see if BIT is getting set properly.
Change-Id: I970ae81ed36da45c3acc61814980b2e6ff889445
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54350
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/mainboard/emulation/qemu-riscv.md')
0 files changed, 0 insertions, 0 deletions