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authorXiang Wang <wxjstz@126.com>2018-08-28 16:34:29 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-09-10 15:03:08 +0000
commit2e38dbe5f1a9db76cdf529679faee63fcb6a9c34 (patch)
tree3656f083f5aad2fc009d1038c313b8cfd695895f /Documentation/lib
parent0370bcf40ce3a07e6e2d33b8bcebf28a0ac98807 (diff)
riscv: update mtime initialization
Add a interface, which is implemented by SoC. Change-Id: I5524732f6eb3841e43afd176644119b03b5e5e27 Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/28372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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