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| author | Patrick Rudolph <siro@das-labor.org> | 2017-10-31 10:49:52 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2018-07-25 13:18:26 +0000 |
| commit | 5ee9bc18407e4c2cad8e1c9e222ca16051d4b9b4 (patch) | |
| tree | a06559c25282d4ca3b0dca9465e5a9a86bac47a8 /Documentation/POSTCODES | |
| parent | 8c85880236d57abf05fb2578a97a3e6dd52e7b7c (diff) | |
nb/intel/sandybridge/raminit: Set REFIx9 according to spec
Set tREFIx9 to 8.9*tREFI/1024 as suggested in
xeon-e3-1200v3-vol-2-datasheet.pdf chapter 4.2.15 or
2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.14.1.
Use the minimum value of REFI*8.9 and tRASmax as suggested by
3rd-gen-core-desktop-vol-2-datasheet.pdf chapter 2.13.9.
Change-Id: Ifd32a70f28aa75418030b0e4d1fc7d539a315f83
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'Documentation/POSTCODES')
0 files changed, 0 insertions, 0 deletions