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authorLean Sheng Tan <lean.sheng.tan@intel.com>2021-06-09 06:51:22 -0700
committerWerner Zeh <werner.zeh@siemens.com>2021-06-30 07:35:32 +0000
commit58ec51cc0aa3795d48b6d692a688017855d11baa (patch)
tree18cbf62f45735681bce2da00960ec6d75841cf82 /Documentation/Intel
parentbed1b602d0cb6027c1b796cb1e44f335e56e0471 (diff)
soc/intel/elkhartlake: Enable PCH GBE
Enable PCH GBE with following changes: 1. Configure PCH GBE related FSP UPD flags 2. Use EHL own GBE ACPI instead of common code version due to different B:D.F from the usual GBE 3. Add kconfig PMC_EPOC to use the PMC XTAL read function Due to EHL GBE comes with time sensitive networking (TSN) capability integrated, EHL FSP is using 'PchTsn' instead of the usual 'PchLan' naming convention across the board. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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