diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2016-07-18 14:13:52 +0530 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@intel.com> | 2016-07-28 05:14:38 +0200 |
| commit | 68d5d8b28ab399b8dfb8ef6477d25311a319f2d5 (patch) | |
| tree | d1442f94451a2a6ac209ab076d9fe879b9e33bf0 /Documentation/Intel/SoC | |
| parent | e3e2bb0a892bc185a52f210bcae15db268c1d034 (diff) | |
soc/intel/skylake: Do cache as ram and prepare for C entry
Enable cache-as-ram and prepare for c entry in bootblock.
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x2A
Credits-to: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I3412216cdf8ef7e952145943d33c3f07949da3c1
Reviewed-on: https://review.coreboot.org/15784
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'Documentation/Intel/SoC')
0 files changed, 0 insertions, 0 deletions