diff options
| author | John Zhao <john.zhao@intel.com> | 2021-01-01 14:19:36 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-08 08:22:47 +0000 |
| commit | 4ead6b33671bba5f67f1cb0d6df5979b47e4ccc0 (patch) | |
| tree | 3f9f760468fcc7d2af07f592b97b1139176e56c3 /Documentation/Doxyfile.coreboot_simple | |
| parent | 81a4c344e7015666b047a05fc0ecb90ad9013d64 (diff) | |
soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports
USB3 is in CPU and USB2 in PCH on Tigerlake. Cross die messaging is
implemented between CPU and PCH through the IOSF SB bridge. a PCH xHCI
USB2 port reset event issued by the xHCI driver shall trigger a message
upstream to CPU to wake it from the low power state which allows a USB3
device that downgraded to USB2 to upgrade back to USB3.
BUG=b:176575892
TEST=Built and booted to kernel on Voxel board.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49052
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'Documentation/Doxyfile.coreboot_simple')
0 files changed, 0 insertions, 0 deletions