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authorMario Scheithauer <mario.scheithauer@siemens.com>2018-11-07 12:58:28 +0100
committerWerner Zeh <werner.zeh@siemens.com>2018-11-12 07:26:02 +0000
commit04ea73ee78bceb680a2565777c4c7774c2ad1a8e (patch)
tree49d9b7070845d26874da5a414ecf3775a024f117 /Documentation/Doxyfile.coreboot
parentd985cdc7638967889e586447fb58a9c14bf72c63 (diff)
siemens/mc_apl3: Set Full Reset Bit into Reset Control Register
This mainboard provides customer hardware reset button. A feature of this button is that it holds the APL in reset state as long as the reset button is pressed. After releasing the reset button the APL should restart again without the need for a power cycle. When Bit 3 in Reset Control Register (I/O port CF9h) is set to 1 and then the reset button is pressed the PCH will drive SLP_S3 active (low). Change-Id: Ib842f15b6ba14851d7f9b1b97c83389adc61f50b Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/29530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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