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authorHannah Williams <hannah.williams@intel.com>2017-03-21 22:34:01 -0700
committerMartin Roth <martinroth@google.com>2017-08-25 18:59:35 +0000
commitad8669ef30743489909cd07be7759b29cf1dbe30 (patch)
tree2cb47e283adf1c7d8f16c55eb226636c2bb969e7 /Documentation/Doxyfile.coreboot
parentaec5e663eb8581aeaadd55661c37bde948a7015e (diff)
soc/intel/braswell: Populate NVS SCC BAR1
Cherry-pick from Chromium commit f92d7be. This BAR is used in _PS0 and _PS3 methods and is used by kernel driver to put SD controller in D3 Original-Change-Id: Iae4722cb222f61e96948265f57d6b522065853d9 Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Tested-by: Aseda Aboagye <aaboagye@chromium.org> Change-Id: I59973226d57fe1dc3da21b2cec1c7b9a713829ab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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