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authorAngel Pons <th3fanbus@gmail.com>2020-07-22 12:47:00 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-08-03 05:27:45 +0000
commite9d1d70c7f0013275de17662a85033b27c06aa5f (patch)
treef8f35028c0f43a5b8af78bfb5a8a57bad7d9c855 /Documentation/AMD-S3.txt
parent0a760cd05b55755510a5672af3a1712a34a7e3aa (diff)
nb/intel/ironlake: Put host bridge registers into its own file
Looks like some registers are defined twice. Also, group some QPI registers together. They were scattered around and mixed with the host bridge registers, probably because other northbridges have such registers in the host bridge's PCI config space. But not Ironlake. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I6e60f7fcb1467f302618eeab1b0d995920a98569 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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